ECE4063 Integrated circuit design
Faculty of Engineering
ECE4063 Integrated circuit design is a level 4, 6-credit-point, undergraduate unit from the Faculty of Engineering, offered in 2026 in Semester 1 at Malaysia. It needs ECE2131 and ECE2072.
- Credit points
- 6
- Offered in 2026
- Semester 1
- Malaysia
- Assessment
- Exam 40%
- and 4 other tasks
- Workload
- 144 hours
- per semester
This is the 2026 handbook entry. See the 2027 entry.
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Requisites
Before ECE4063
Prerequisites
Pass these before you enrol.
Prohibitions
You can't enrol if you have passed any of these.
After ECE4063
No unit lists ECE4063 as a prerequisite in the 2026 handbook.
Equivalent units
The same content under another code. Only one of them counts.
Overview
The unit aims to develop a fundamental understanding of the performance, specification and fabrication of large scale digital circuits. You will become experienced at the design, simulation, verification and debugging of complex large scale digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. Two group design projects will be undertaken: one involving an HDL using FPGA devices and another involving custom VLSI CMOS design and simulation
Offerings in 2026
| Teaching period | Campus | Mode |
|---|---|---|
| First semester | Malaysia | On campus |
Assessment
- Workshop activitiesExerciseThreshold hurdle10%
- Mid-semester testQuiz / TestThreshold hurdle10%
- Laboratory activitiesDemonstrationThreshold hurdle25%
- ProjectThreshold hurdle15%
- Final assessmentExaminationThreshold hurdle40%
Assessment details may change. Please refer to the assessment information in Moodle closer to the start of the teaching period.
Learning outcomes
When you finish this unit, you should be able to:
- 1
Describe the fabrication processes used for producing CMOS VLSI circuits.
- 2
Apply the principles of CMOS Digital Circuits in case studies and problems.
- 3
Draw a CMOS layout and assess the design in terms of speed, power and area.
- 4
Predict and optimise the delay in multiple paths of a VLSI design.
- 5
Design, implement and debug a complex digital design using HDL as part of a team.
Workload and teaching
- Workshops24 hours
- Laboratories24 hours
The minimum total expected workload to achieve the learning outcomes for this unit is 144 hours per semester typically comprising a mixture of 3-6 hours of scheduled learning activities and 6-9 hours of independent study per week. Scheduled activities may include a combination of teacher-directed learning, peer-directed learning and online engagement. Independent study may include associated readings, assessment and preparation for scheduled activities.
Where it fits
ECE4063 is part of 2 areas of study in the 2026 handbook.
Contacts
- Chief Examiners
- Dr Patrick Ho
- Unit Coordinators
- Dr Patrick Ho
Common questions
When is ECE4063 offered?
In 2026, ECE4063 runs in Semester 1 at Malaysia.
How much work is ECE4063?
The handbook expects about 144 hours of study across the semester. No students have rated its difficulty yet.
Does ECE4063 have an exam?
Yes. The exam is worth 40% of the final mark, alongside 4 other tasks.
Which majors and minors include ECE4063?
ECE4063 is part of Electrical and computer systems engineering; and Semiconductor.