ECE5063 Integrated circuit design
Faculty of Engineering
ECE5063 Integrated circuit design is a level 5, 6-credit-point, postgraduate unit from the Faculty of Engineering, offered in 2026 in Semester 1 at Malaysia. It has no prerequisites.
- Credit points
- 6
- Offered in 2026
- Semester 1
- Malaysia
- Assessment
- No exam
- 4 tasks
- Workload
- 144 hours
- per semester
The 2027 handbook has no page for ECE5063. This is its 2026 entry, the latest one.
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Requisites
Before ECE5063
Prohibitions
You can't enrol if you have passed any of these.
After ECE5063
No unit lists ECE5063 as a prerequisite in the 2026 handbook.
Enrolment rules
You must be currently enrolled in a master’s course in engineering or related STEM and in a related discipline. The unit assumes that you have the necessary foundational knowledge.
Equivalent units
The same content under another code. Only one of them counts.
Overview
This unit helps you build a solid understanding of the performance, specification, and fabrication of large-scale digital circuits, including MOS transistor principles, CMOS inverters, building blocks, and interconnects. You’ll explore how to design, simulate, verify, and debug complex digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. You’ll also become familiar with very large-scale integrated (VLSI) circuit design flow methodologies, including layout placement, partitioning, floor planning, and routing.
Offerings in 2026
| Teaching period | Campus | Mode |
|---|---|---|
| First semester | Malaysia | On campus |
Assessment
- Workshop activitiesExercise10%
- Mid-semester testQuiz / Test15%
- Laboratory activitiesDemonstration35%
- Project40%
Assessment details may change. Please refer to the assessment information in Moodle closer to the start of the teaching period.
Learning outcomes
When you finish this unit, you should be able to:
- 1
Discuss and evaluate the design process of IC circuits in the semiconductor industry.
- 2
Apply and analyse the principles of CMOS Digital Circuits in case studies and problems.
- 3
Construct a CMOS layout and assess the design in terms of speed, power and area.
- 4
Analyse and evaluate the delay in multiple paths of a VLSI design.
- 5
Design a customised IC circuit based on an industrial design case study and perform full verification on the design for manufacturability.
Workload and teaching
- Laboratories24 hours
- Workshops24 hours
- Teaching approachProblem-based learning
The minimum total expected workload to achieve the learning outcomes for this unit is 144 hours per semester typically comprising a mixture of 3-6 hours of scheduled learning activities and 6-9 hours of independent study per week. Scheduled activities may include a combination of teacher-directed learning, peer-directed learning and online engagement. Independent study may include associated readings, assessment and preparation for scheduled activities
This unit includes case-based teaching, where you will apply your knowledge and engage in analytical and reflective thinking to solve complex contextual scenarios. Activities are often designed so that there is no single clear answer, but you will work with your peers to examine, analyse and make decisions to resolve the situation.
Where it fits
ECE5063 is part of 1 area of study in the 2026 handbook.
Contacts
- Unit Coordinators
- Dr Patrick Ho
- Chief Examiners
- Dr Patrick Ho
Common questions
What are the prerequisites for ECE5063?
ECE5063 has no prerequisites, but enrolment rules apply.
When is ECE5063 offered?
In 2026, ECE5063 runs in Semester 1 at Malaysia.
How much work is ECE5063?
The handbook expects about 144 hours of study across the semester. No students have rated its difficulty yet.
Does ECE5063 have an exam?
No. ECE5063 has 4 assessment tasks and no exam.
Which majors and minors include ECE5063?
ECE5063 is part of Semiconductor and microsystems engineering .
More details
- Credit points
- 6
- Level
- 5
- Study level
- Postgraduate
- Faculty
- Faculty of Engineering
- Organisational unit
- Malaysia School of Engineering
- Type
- Coursework
- EFTSL
- 0.125
- Student contribution
- SCA Band 2
- Study abroad
- Available
- Handbook years
- 2026